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ATmega128A MCUCR - MCU Control Register

Edited by waveshare, NOT allowed to be copied or transferred.

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.

• Bit 6 – SRW10: Wait-state Select Bit

For a detailed description in non-ATmega103 compatibility mode, see common description for the SRWn bits below (XMCRA description). In ATmega103 compatibility mode, writing SRW10 to one enables the wait-state and one extra cycle is added during read/write strobe as shown in Figure 7-7.

ATmega128A XMCRA - External Memory Control Register A

• Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices.

• Bit 6:4 – SRL2, SRL1, SRL0: Wait-state Sector Limit It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 7-3 and Figure 7-4. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.

Table 7-3. ATmega128A Sector limits with different settings of SRL2:0

• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space, see Table 7-4.

• Bit 3:2 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the external memory address space, see Table 7-4.

Table 7-4. ATmega128A Wait States(1)

Note: 1. n = 0 or 1 (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see Figures 7-6 through Figures 7-9 for how the setting of the SRW bits affects the timing.

• Bit 0 – Res: Reserved Bit

This is a reserved bit and will always read as zero. When writing to this address location, write this bit to zero for compatibility with future devices.

ATmega128A XMCRB - External Memory Control Register B

• Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one.

• Bit 6:4 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.

• Bit 2:0 – XMM2, XMM1, XMM0: External Memory High Mask
When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 7-5. As described in "Using all 64KB Locations of External Memory" on page 28, it is possible to use the XMMn bits to access all 64KB locations of the External Memory.

Table 7-5. ATmega128A Port C Pins Released as Normal Port Pins when the External Memory is Enabled

Table 7-5.ATmega128A Port C Pins Released as Normal Port Pins when the External Memory is Enabled